The present invention relates to a semiconductor design technology, and more particularly, to a pipe latch circuit for serializing a plurality of data in a predetermined order to output the serialized data, and a driving method thereof.
A semiconductor memory device such as Double Data Rate Synchronous DRAM (DDR SDRAM) has been advanced for achieving high speed data processing and large storage capacity. A conventional semiconductor memory device such as a Single Data Rate Synchronous DRAM (SDR SDRAM) outputs a plurality of data by synchronizing the data with a rising edge of an external clock signal. However, the semiconductor memory device such as a DDR SDRAM outputs a plurality of data by synchronizing the data not only with a rising edge but also with a falling edge of an external clock signal. That is, the DDR SDRAM can process data twice as much as the SDR SDRAM at the same frequency of the external signal.
Meanwhile, a semiconductor memory device includes a pipe latch circuit for effectively processing data. The pipe latch circuit latches a plurality of data stored in memory cells in the semiconductor memory device, receives data in an order corresponding to the address information, and outputs data in response to a synchronization clock signal. Here, latching a plurality of data is referred as pre-fetch. For example, 2-bit pre-fetch means that two data are latched by one read command. 4-bit pre-fetch means that four data are latched by one read command. The latched data are inputted in a predetermined order corresponding to address information and outputted after being synchronized with a synchronization clock signal. The pipe latch circuit enables the semiconductor memory device to process a large amount of data at a high speed through the above described operation of the pipe latch circuit.
Meanwhile, the semiconductor memory device includes about ten million memory cells for storing data. The semiconductor memory device stores or outputs data according to a command from a central processing unit CPU. That is, the semiconductor memory device stores data at a memory cell corresponding to an address inputted from the CPU when the CPU requests a write operation. Also, the semiconductor memory device outputs data stored in a memory cell corresponding to an address inputted from the CPU when the CPU requests a read operation. In the write operation, data inputted through an input/output pad is inputted to a memory cell through a data input path. In the read operation, data stored in a memory cell is outputted to an external device through the input/output pad after passing through a data output path.
The semiconductor memory device receives a read command that is synchronized with an external clock signal in the read operation and outputs data synchronized with an internal clock signal to the outside. That is, the semiconductor memory device uses the internal clock signal to output data instead of using the external clock signal. Therefore, the semiconductor memory device must generate an internal command by synchronizing the read command synchronized with the external clock signal with the internal clock signal in the read operation. Here, synchronizing a signal, which is synchronized with one clock, with the other clock, like the read command, is referred as domain crossing.
The semiconductor memory device includes a plurality of circuits for performing the domain crossing operation, and a domain crossing performed signal corresponding to a read command is referred as an “output enable signal”. The output enable signal is synchronized with an internal clock signal and includes CAS latency information. Here, the CAS latency includes information on time duration from a time of applying a read command to a time of outputting corresponding data in a unit time of one cycle of an external clock signal. The semiconductor memory device employs the output enable signal to output data synchronized to an external clock signal at a target time after the read command.
A skew between an external clock signal and an internal clock signal may be generated by delay components in the semiconductor memory device. In order to correct the skew, the semiconductor memory device includes an internal clock signal generating circuit. The internal clock signal generating circuit includes a phase locked loop and a delay clock loop (DLL). In the specification, a DLL clock signal generated from the delay lock loop (DLL) will be used as the internal clock signal. The DLL clock signal is used as a reference for synchronizing data in the semiconductor memory device.
FIGS. 1A and 1B are circuit diagrams illustrating a part of a conventional pipe latch circuit. The conventional pipe latch circuit may include a rising pipe latch unit 110R corresponding to a rising edge of a DLL clock signal, shown in FIG. 1A, and a falling pipe latch unit 110F corresponding to a falling edge of a DLL clock signal, shown in FIG. 1B.
Referring to FIG. 1A, the rising pipe latch unit 110R receives zeroth to seventh data MXOUT<0:7> in an order corresponding to address information and outputs a rising output signal RDOB in response to a rising output control signal RPOUT. The rising pipe latch unit 110R includes a rising pipe input unit 111R, a first rising selection output unit 113R, a second rising selection output unit 115R and a rising output unit 117R.
The rising pipe input unit 111R outputs corresponding data of the zeroth to seventh data MXOUT<0:7> to zeroth to third rising nodes NR0, NR1, NR2 and NR3 in response to even control signals START_EV and START_EVB and odd control signals START_OD and START_ODB. Each control signal controlling the rising pipe input unit 111R will be described later with reference to FIG. 2.
The first rising selection output unit 113R outputs data applied to corresponding node among the zeroth to third rising nodes NR0, NR1, NR2, and NR3 to fourth and fifth rising nodes NR4 and NR5 in response to a first rising order selection signal SOSESR1R_B. The second rising selection output unit 115R outputs data applied to the fourth and fifth rising nodes NR4 and NR5 in response to a second rising order selection signal SOSEB2R_B.
The first and second rising order selection signals SOSEB1R_B and SOSEB2R_B controlling the first and second rising selection output units 113R and 115R will be described again with reference to FIG. 2.
The rising output unit 117R outputs an output signal of the second rising selection output unit 115R as the rising output signal RDOB in response to the rising output control signal RPOUT. The rising output control signal RPOUT will be described again with reference to FIG. 2.
Referring to FIG. 1B, the falling pipe latch unit 110F receives zeroth to seventh data MXOUT<0:7> in an order corresponding to address information and outputs a falling output signal FDOB in response to a falling output control signal FPOUT. The falling pipe latch unit 110F includes a falling pipe input unit 111F, a first falling selection output unit 113F, a second falling selection output unit 115F and a falling output unit 117F.
The falling pipe input unit 111F outputs corresponding data among zeroth to seventh data MXOUT<0:7> to zeroth to third falling nodes NF0, NF1, NF2, and NF3 in response to even control signals START_EV and START_EVB and odd control signals START_OD and START_ODB. Each control signal for controlling the falling pipe input unit 111F will be described again with reference to FIG. 2.
The first falling selection output unit 113F outputs data applied to a corresponding node among the zeroth to third falling nodes NF0, NF1, NF2, and NF3 to fourth and fifth falling nodes NF4 and NF5 in response to a first falling order selection signal SOSEB1F_B. The second falling selection output unit 115F outputs data applied to the fourth or fifth falling nodes NF4 and NF5 in response to the second falling order selection signal SOSEB2F_B. The first and second falling order selection signals SOSEB1F_B and SOSEB2F_B for controlling the first and second falling selection output units 113F and 115F will be described again with reference to FIG. 2.
The falling output unit 117F outputs an output signal of the second falling selection output unit 115F as the falling output signal FDOB in response to the falling output control signal FPOUT. The falling output control signal FPOUT will be described again with reference to FIG. 2.
FIG. 2 is a circuit diagram illustrating a control signal generator for generating signals that controls a rising pipe latch unit 110R and a falling pipe latch unit 110F shown in FIGS. 1A and 1B.
As shown, the control signal generator includes an odd/even control signal generator 210, a rising control signal generator 230R and a falling control signal generator 230F.
The odd/even control signal generator 210 generates even control signals START_EV and START_EVB and odd control signals START_OD and START_ODB in response to a pipe enable signal PINB and a zeroth order deciding signal SOSEB<0>.
The pipe enable signal PINB is activated in response to a time point of delaying as long as an asynchronous time a control signal for controlling applying data stored in a memory cell to a global data line. The control signal controls the data to be applied to the global data line after the data stored in the memory cell is transferred from a bit line to a local data line. Then, the zeroth order deciding signal SOSEB<0> is a signal corresponding to a zeroth address applied in a read operation. Finally, the odd/even control signal generator 210 is enabled in response to the pipe enable signal PINB and activates the even control signals START_EV and START_EVB or the odd control signals START_OD and START_ODB according to the zeroth order deciding signal SOSEB<0>.
The rising control signal generator 230R generates the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B in response to first and second rising order deciding signals SOSEB_R<1> and SOSEB_R<2>) and the rising output control signal RPOUT. The rising output control signal RPOUT is a signal for controlling an output period of the rising pipe latch unit 110R (see FIG. 1). The first and second rising order deciding signals SOSEB_R<1> and SOSEB_R<2> are signals for toggling according to first and second addresses applied in a read operation. Finally, the rising control signal generator 230R is enabled in response to the rising output control signal RPOUT and outputs the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B in response to the first and second rising order deciding signal SOSEB_R<1> and SOSEB_R<2> as shown in FIG. 3.
The falling control signal generator 230F generates the first and second falling order selection signals in response to the falling output control signal FPOUT and first and second falling order deciding signals SOSEB_F<1> and SOSEB_F<2>. Here, the falling output control signal FPOUT is a signal controlling an output period of the falling pipe latch unit 110F (See FIG. 1). The first and second falling order deciding signals SOSEB_F<1> and SOSEB_F<2> are signals for toggling according to first and second addresses applied in the read operation. Finally, the falling control signal generator 230F is enabled in response to the falling output control signal FPOUT and outputs the first and second falling order selection signals SOSEB1F_B and SOSEB2F_B in response to the first and second falling order deciding signals SOSEB_F<1> and SOSEB_F<2> as shown in FIG. 3.
FIG. 3 illustrates waveforms of signals in a read operation, shown in FIGS. 1A, 1B and 2. For illustration purposes, it may be assumed that the zeroth to second addresses are applied as ‘000’. If the zeroth to second addresses are applied as ‘000’, pre-fetched zeroth to seventh data MXOUT<0:7> are outputted through an input/output pad DQ in an order of the zeroth data XMOUT<0>→the first data XMOUT<1>→the second data XMOUT<2>→the third data XMOUT<3>→the fourth data XMOUT<4>→the fifth data XMOUT<5>→the sixth data XMOUT<6>→the seventh data XMOUT<7>.
Here, FIGS. 1A, 1B, 2 and 3 illustrate circuits and timing diagrams of a semiconductor memory device supporting an 8-bit pre-fetch operation. The pipe latch circuit decides an output order of the zeroth to seventh data MXOUT<0:7> using a zeroth order deciding signal SOSEB<0> corresponding to a zeroth address, first rising and falling order deciding signals SOSEB_R<1> and SOSEB_F<1> corresponding to a first address, and second rising and falling order deciding signals SOSEB_R<2> and SOSEB_F<2> corresponding to a second address. In other words, the pipe latch circuit pre-fetches eight data, the zeroth to seventh data MXOUT<0:7> and sequentially outputs the pre-fetched eight data corresponding to three addresses. For example, in case of a semiconductor memory device supporting a 4-bit pre-fetch operation, the pipe latch circuit pre-fetches four data and sequentially outputs the pre-fetched data corresponding to two addresses.
The semiconductor memory device starts outputting data at a time corresponding to CAS latency CL after a read command RD. Here, the zeroth to seventh data XMOUT<0:7> are outputted to the input/output pad DQ in response to a rising clock signal RCLKDO corresponding to a rising edge of a DLL clock signal CLK_DLL and a falling clock signal FCLKDO corresponding a falling edge of the DLL clock signal CLK_DLL. The rising clock signal RCLKDO and the falling clock signal FCLKDO are generated based on an output enable signal and a DLL clock signal CLK_DLL corresponding to the rising edge and the falling edge of the DLL clock signal CLK_DLL.
Hereinafter, operation of a semiconductor memory device will be described with reference to FIGS. 1A, 1B, 2 and 3.
In response to the read command RD, the pipe enable signal PINB is activated to logic ‘low’ level. Here, since the zeroth order deciding signal SOSEB<0> is 0, the even control signal START_EV is activated to logic ‘high’ level, and the even control signal bar START_EVB is activated to logic ‘low’ level.
Therefore, the rising pipe input unit 111R outputs the zeroth data MXOUT<0> to the zeroth rising node NR0, outputs the second data MXOUT<2> to the first rising node NR1, outputs the fourth data MXOUT<4> to the second rising node NR2, and outputs the sixth data MXOUT<6> to the third rising node NR3.
Meanwhile, the rising output control signal RPOUT and the falling output control signal FPOUT are activated to logic ‘high’ level in response to a DLL clock signal CLK_DLL corresponding to the CAS latency CL. Here, the rising output control signal RPOUT is activated in response to a falling edge of the DLL clock signal CLK_DLL which is ahead of the CAS latency by a half clock. The falling output control signal is activated in response to a rising edge of the DLL clock signal CLK_DLL corresponding to the CAS latency CL. The rising output control signal RPOUT and the falling output control signal FPOUT are inactivated after four tCKs in consideration that a burst length is 8. For example, if a burst length is 4, the rising output control signal RPOUT and the falling output control signal FPOUT are inactivated after 2tCK.
The rising control signal generator 230R outputs the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B according to the first and second rising order deciding signals SOSEB_R<1> and SOSEB_R<2>. That is, the first rising order selection signal SOSEB1R_B is synchronized with a falling edge of a DLL clock signal CLK_DLL which is ahead of the CAS latency CL by a half clock in an activation period of the rising output control signal RPOUT and is toggled in 1tCK-by-1tCK basis. The second rising order selection signal SOSEB2R_B is synchronized with a falling edge of the DLL clock signal that the rising order selection signal SOSEB1R_B is synchronized with in an activation period of the rising output control signal RPOUT and is toggled in 2 tCK-by-2 tCK basis. As shown, the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B have sequentially have values of (1,1)→(0,1)→(1,0)→(0,0) in 1tCK-by-1tCK basis. For reference, the toggling times of the first and second rising order selection signals SOSEB1R_B and SOSER2R_B are decided by the first and second addresses.
Hereinafter, when the first and second rising order selection signals SOSEB1R_Band SOSEB2R_B have a value of (1,1), the related operation of a pipe latch circuit will be described.
The first rising selection output unit 113R outputs the zeroth data MXOUT<0> applied to the zeroth rising node NR0 to the fourth rising node NR4 and outputs the fourth data XMOUT<4> applied to the second rising node NR2 to the fifth rising node NR5. The second rising selection output unit 115R outputs the zeroth data MXOUT<0> applied to the fourth rising node NR4. Finally, the rising output unit 117R outputs the zeroth data MXOUT<0> as the rising output signal RDOB.
When the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B have a value of (0,1), the second data MXOUT<2> is outputted as the rising output signal RDOB through corresponding operation to the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B. When the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B have a value of (1,0), the fourth data MXOUT<4> is outputted as the rising output signal RDOB. When the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B have a value of (0,0), the sixth data MXOUT<6> is outputted as the rising output signal RDOB. That is, the rising output signal RDOB transits to the zeroth data MXOOUT<0>→the second data MXOOUT<2>→the fourth data MXOOUT<4>→the sixth data MXOOUT<6>.
The falling pipe latch unit 110F performs the similar operation of the rising pipe latch unit 110R in response to output signals of the odd/even control signal generator 210 and the falling control signal generator 230F. The falling output signal FDOB transits to the first data MXOUT<1>→the third data MXOUT<3>→the fifth data MXOUT<5>→the seventh data MXOUT<7>. If operating times of the rising pipe latch unit 110R and the falling pipe latch unit 110F are considered, the input/output pad DQ sequentially outputs data in order of the zeroth data XMOUT<0>→the first data XMOUT<1>→the second data XMOUT<2>→the third data XMOUT<3>→the fourth data XMOUT<4>→the fifth data XMOUT<5>→the sixth data XMOUT<6>→the seventh data XMOUT<7>.
Meanwhile, semiconductor memory devices have been advanced for high data processing, and an operating frequency of the semiconductor memory device has been increasing. The high operation frequency may cause problems that were not generated in a semiconductor memory device having a comparatively low operation frequency. As an example of the problems, a data margin problem of data that is synchronized with a clock signal corresponding to the operation frequency has been receiving attention.
Referring to FIGS. 1 and 3 again, four control signals are used to output the rising output signal RDOB in the rising pipe latch unit 110R. That is, the rising pipe input unit 111R is controlled by the even control signals START_EV and START_EVB, and odd control signals START_OD and START_ODB. The first rising selection output unit 113R is controlled by the first rising selection signal SOSEB1R_B, the second rising selection output unit 115R is controlled by the second rising selection signal SOSEB2R_B, and the rising output unit 117R is controlled by the rising output control signal RPOUT.
Since the even control signals START_EV and START_EVB and the odd control signals START_OD are START_ODB are activated in response to the pipe enable signal PINB, the even control signals START_EV and START_EVB and the odd control signals START_OD and START_ODB are activated before a time of outputting a plurality of data. A problem occurs by a control signal of the first rising selection output unit 113R, the second rising selection output unit 115R and the rising output unit 117R.
More specifically, the first and second rising order selection signals SOSEB1R_B and SOSEB2R_B are synchronized with the DLL clock signal CLK_DLL in an activation period of the rising output control signal RPOUT as shown in FIG. 2. Therefore, when the rising output unit 117R is enabled in response to the rising output control signal RPOUT, the first and second rising selection output units 113R and 115R, which are controlled by the first and second order selection signals SOSEB1R_B and SOSEB2R_B, are enabled, and data are transferred in a corresponding order. Therefore, the rising output signal RDOB outputted from the rising output unit 117R may output garbage data while transferring data through the first and second rising selection output units 113R and 115R.
Such a problem similarly occurs when the falling pipe latch unit 110F outputs the falling output signal FDOB, and reduces a valid data window of the rising output signal RDOB and the falling output signal FDOB. The valid data window may be further reduced by a skew generated according to a process, a voltage and a temperature. Finally, the valid data window of data outputted as the rising output signal RDOB and the falling output signal FDOB of the pipe latch circuit become smaller. That is, a margin of the rising clock signal RCLKDO and the falling clock signal FCLKDO shown in FIG. 2 becomes smaller. Finally, such a margin problem may cause an error that makes the semiconductor memory device to inaccurately output data.